1. Field of the Invention
The invention relates to a method for fabricating a hemispherical grain (HSG) electrode, and more particular to a method of increasing the surface area of a storing node by forming a blanket HSG silicon (HSG-Si) layer on the bottom electrode, to obtain a higher capacitance of a capacitor in a dynamic random access memory (DRAM).
2. Description of the Related Art
In a DRAM, the typical method to access data is by charging or discharging optionally into each capacitor of the capacitor array on the semiconductor substrate.
Due to the higher and higher integration of IC, dimensions of devices or structures (such as transistors, capacitors) become smaller and smaller. Thus, the storage of charges (that is, the capacitance) of the capacitor in the design of a conventional planar capacitor decreases. The decrease of charge storage causes various problems, including mechanical deterioration and charge leakage by the larger susceptibility, and therefore, causes potential loss. The charge leakage caused by larger susceptibility may cause more frequent refresh period, and by which, memory can not handle data saving and reading properly. Moreover, the decrease of charge storage may need more complex data reading plan, or more sensitive charge induction amplifier.
Up to now, there are three ways to solve the problem of low capacitance of a capacitor resulted from the higher integration in a very large scaled integrated circuit. The first method is to reduce the thickness of the dielectric layer between two conductors of the capacitor. It is known that the capacitance is proportional to the inverse of distance between two conductors in a capacitor. Thus, the decrease of the thickness of dielectric layer increases the capacitance effectively. However, according to the consideration of the uniformity and stability of the dielectric layer, this is a method difficult to control. The second method, which is the most direct method, is to adapt the material with high dielectric constant, such as, tantalum oxide (Ta.sub.2 O.sub.5), as the dielectric layer. However, the high leakage current and low breakdown voltage caused by the atomic arrangement of tantalum oxide still needs to be improved. The third method is to increase the surface area of the storage node of the capacitor. The capacitance is proportional to the surface area of storage node, that is, the conductor (electrode). Therefore, to increase the surface area of the storage node increases the capacitance as well. The very common structure for increasing the surface area is the fin-shape or the box-shape structure. These kinds of structures are complex for fabrication, and thus, cause the difficulty in mass production. Another structure with a larger surface area is the HSG structure.
FIG. 1a and FIG. 1b show a conventional process of fabricating an HSG-Si bottom electrode. Referring to FIG. 1a, on an oxide layer 100, a doped poly-silicon layer 102 is formed. A blanket HSG-Si layer 104 is formed on the doped poly-silicon layer 102. Using photolithography and etching process, the blanket HSG-Si layer 104 is patterned to form a bottom electrode 104a. As shown on FIG. 1b, in the conventional process, the HSG structure is formed on the top surface of the electrode only. The side wall of the electrode is flat, and thus, the surface gain of capacitance obtained by the formation of the HSG structure is limited.